1. Field of the Invention
This invention relates generally to computer processor memory storage systems and more particularly to self managing memory systems that vertically slice the storage hierarchy for increased virtual memory giving the appearance of an extended secondary cache to the processor.
2. Description of the Related Art
As processors continue to get faster, memory continues to get more dense and its speed continues to lag that of the processor. This gap between processor and memory access speed has given rise to hierarchical memory architectures that attempt to smooth the technological discontinuities. Current processor strategy requires the central processing unit (CPU) to have on-chip primary cache memory with a secondary cache located in close proximity. Both primary and secondary caches are normally static random access memory (SRAM) technology and must be leading-edge for best performance. From the processor's view, maximum performance with respect to memory operations is obtained when no memory "wait states" are caused due to information not being present in the cache. When information is not in the cache, it must be fetched from the next memory level. The actual penalty for a failure of the processor to find the desired information in the cache, or cache miss, will be a certain amount of time depending on the memory block size as well as memory latency and bandwidth.
Virtual memory allows the creation of the illusion of a large memory that can be accessed as fast as a small memory. The principle of locality governs the behavior of virtual memory systems. Locality is exhibited spatially, as well as temporally. Spatial locality arises due to the clustering effect of the executing program and data in memory. Items with addresses close to a referenced item are likely to be also referenced. Temporal locality arises due to the fact that when an item that is referenced once, it is likely to be referenced soon again.
The benefits of virtual memory are efficient sharing of memory between multiple programs, the ability to exceed the size of the primary memory while making data movement between small physical memory and large secondary memory transparent to the user and the ability to dynamically relocate program address space.
While the transfers between cache and main memory are handled mostly in hardware, transfers between disks and main memory are typically managed by the operating system in the CPU. The disk subsystem, memory bus and I/O control are shared by the main memory subsystem to implement a typical virtual memory. Similarly, the same main memory is shared by the cache over the main memory bus to implement the next level of hierarchy. This sharing of resources over a limited bandwidth bus causes severe performance bottlenecks.
The ability to package systems that interconnect logic and memory is known in the art. This is typically done via multichip module technology as described in King L. Tai, et al., "A Chip-On-Chip DSP/SRAM Multichip Module", Proceedings International Conference on Multichip Modules, Denver, Colo., Apr. 19-21 (1995). Silicon-on silicon multichip modules allow for the micro-integration of various memories on a single module with the additional logic for control.